#26
#25
GraphSAGE-Based Partial Scan Flip-Flop Selection for High Test Coverage
#24
Reliability-Driven Redundancy Analysis for Interleaved-ECC Memory Repair
#23
WTM-Aware Shift Direction Selection for Low Power Bidirectional Scan Testing
#22
A New Dual-Engine Error Recovery Scheme for High-Reliability HBM
#21
Directional Fault Masking Scheme for Radiation-Resilient LUTs
#20
A Two-Phase Test Point Insertion Scheme for Low-Power Scan Testing
#19
Error-Correction Circuit based PUF Structure for High Reliability SSN
#18
SDC-aware Masking Scheme for Biased SEUs and Directional Bit-Flipping
#17
A Self-Recovery Scheme for Fault Tolerance and Side-Channel Resistance in Systolic Arrays
#16
Optimized Instruction Set Architecture for Programmable Memory Test Pattern Generation
#15
Production-Oriented Design for High Parallel Test Efficiency
#14
Reduced Pin-Count Test Scheme for High Parallel Test Capabilities
#13
Output Compression Scheme of Multi-Site Testing for System-on-Chip
#12
Instruction-based March Test Pattern Generation Scheme for At-Speed Test Cost Reduction
#11
Tunable Compact Probing Detector with Fast Analysis Time Against Invasive Attacks
#10
2-D failure bitmap compression using line fault marking method
#09
An Efficient Built-in Self-Repair Scheme for Area Reduction
#08
Test Item Priority Estimation for High Parallel Test Efficiency under ATE Debug Time Constraints
#07
A Test Methodology to Screen Scan-Path Failures
#06
A TSV Test Structure for Simultaneously Detecting Resistive Open and Bridge Defects in 3D-ICs
#05
A Study on Automatic SPI ROM Version Updates for Production
#04
A Study on SPI ROM Write Function with DSSC
#03
A Study on SPI ROM Slave Protocol Aware
#02
New Test Technique for Substituting Serial Measurement with Matrix Measurement
#01