#I14
국제논문지 (International Journal)
#I13
Scalable Multi-Site Test Architecture for Chiplet-Based Systems on ATE Platforms
#I12
Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip
#I11
Timestamp-Based Secure Shield Architecture for Detecting Invasive Attacks
#I10
Row Hammer Reduction Using a Buried Insulator in a Buried Channel Array Transistor
#I09
4-Pole Hybrid HVDC Circuit Breaker for Pole-to-Pole Fault Protection
#I08
Reduced-Pin-Count BOST for Test-Cost Reduction
#I07
Robust Secure Shield Architecture for Detection and Protection Against Invasive Attacks
#I06
Advanced Low Pin Count Test Architecture for Efficient Multi-Site Testing
#I05
A Low-cost Concurrent TSV Test Architecture with Lossless Test Output Compression Scheme
#I04
An Efficient BIRA Utilizing Characteristics of Spare Pivot Faults
#I03
Test Resource Reused Debug Scheme to Reduce the Post-Silicon Debug Cost
#I02
A Statistic-based Scan Chain Reordering for Energy-Quality Scalable Scan Test
#I01
Grouping-based TSV Test Architecture for Resistive Open and Bridge Defects in 3D-ICs
국내논문지 (Domestic Journal)
#D05
메모리 테스트 패턴 호환성 향상을 위한 고급언어 컴파일러 구조
#D04
비트맵 데이터 학습을 통한 딥러닝 기반의 메모리 수리 예측 기술 연구
#D03
광학 문자 인식 기술을 활용한 점자 변환 시스템의 설계 및 구현
#D02
교통사고 저감을 위한 인공지능 기반 인캐빈 모니터링 시스템
#D01